Low-power optimization of selected FPGA blocks

Reconfigurable logic can offer a wide range of flexibility for different applications. Since the introduction of the first FPGAs by a number of different companies, they were used as glue logic to connect different components of an entire system. In the following years, fast prototyping has led to new possibilities of firmware development running in parallel to IC design, and because of that, the development time has been reduced significantly and products can enter the market at an earlier point of time. However, these special ICs cannot compete with ASICs in mass production due to their high production costs which consequently limits their application to cost sensitive markets e. g. for being used in automotive applications. This has led various FPGA vendors to develop low-end FPGAs for countering the price advantage of ASICs and to raise the attractiveness of these chips in the automotive industry. Despite many advantages of reconfigurable logic, cost-optimized FPGAs lack of efficient power saving mechanisms which is a necessary feature in applications with limited energy resources. The scope of this thesis is the research on the implementation of dedicated power saving logic on selected blocks within a FPGA. These blocks were analyzed based on the choice of a commercial baseline architecture and re-engineered to significantly cut-down the average power consumption and related leakage currents. The affected blocks were SRAM cells, D-FFs and I/O elements, which consume a comparably large area footprint of the FPGA fabric and therefore depict a good target for optimization and modification. Specific characteristics like SNM, WNM, maximum frequency and high impedance were also considered and evaluated against the baseline design as well as compared against selected solutions from related academic research.