Aspects of analog-to-digital conversion in modern receiver architectures

The design paradigm for wireless radio terminals has experienced major changes in the last decades. Novel transceiver design principles encourage to move the digital signal processing closer to the antenna while reducing the amount of analog off-chip components. This design methodology gives the ability to built fully reconfigurable radios which are capable of operating at any frequency band and with any communication standard. As a consequence thereof, the requirements on the remaining analog components increases while the overall power consumption of the radio has to remain at the same level. A key component in every modern receiver architecture is the Analog-to-Digital Converter (ADC). It faces even tougher specifications in the sampling rate and the quantization resolution compared to conventional receivers due to the reduced analog processing. In this work, we investigate the process of analog-to-digital conversion in the light of direct bandpass (BP) signal sampling in detail. The behavior at each stage of the ADC is studied, basic performance limitations are discussed and a framework to determine feasible parameters is proposed. This work simplifies the parameterization of the bandpass sampling ADC (BP-ADC) and can be used to explore novel aspects in receiver design. For this purpose, the ADC is split into its two basic blocks: sampling and quantization. For BP sampling, the sampling stage is of fundamental importance as it deals with the time-discretization and the down-conversion of the desired signal simultaneously. In particular, we focus on the impact of realistic sampling circuits, i. e., sample-and-hold or track-and-hold, on the signal-to-noise ratio (SNR) of the desired receive signal. Furthermore, the problem of sampling jitter is investigated and its limitations on the SNR of the BP-ADC are shown. Finally, a framework to find feasible ADC configurations is proposed. It was found that considering the filter characteristics of the sampling circuit is indispensable for BP-ADCs. This property was often neglected for such applications. Moreover, the BP-ADC needs to comply with the certain sampling jitter requirements and a minimum quantization resolution to ensure a predefined noise figure of the receiver. The obtained sets of feasible ADC parameters give a prediction on the expected power consumption and allows the selection of an appropriate ADC topology. This work is enhanced by an advanced receiver architecture, which inherently compensates random phase rotations due to imperfect down-conversion mixing with jittered sampling. It is shown that using a shared clock signal with the same phase noise realization for the mixer and sampler dramatically improves the SNR performance of the receiver without any additional digital post-processing.